Insulating buffer film and high dielectric constant semiconductor device and method for fabricating the same

ABSTRACT

A semiconductor device includes: an n-transistor including a first gate insulating film made of a high-dielectric-constant material and a first gate electrode fully silicided with a metal, the first gate insulating film and the first gate electrode being formed in this order over a semiconductor region; and a p-transistor including a second gate insulating film made of the high-dielectric-constant material and a second gate electrode fully silicided with the metal, the second gate insulating film and the second gate electrode being formed in this order over the semiconductor region. If the metal has a work function larger than a Fermi level in potential energy of electrons of silicon, a metal concentration of the second gate electrode is higher than that of the first gate electrode whereas if the metal has a work function smaller than the Fermi level of silicon, a metal concentration of the second gate electrode is lower than that of the first gate electrode.

CROSS-REFERENCE TO RELATED APPLICATION

The disclosure of Japanese Patent Application No. 2005-170208 filed onJun. 9, 2005 including specification, drawings and claims isincorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

The present invention relates to methods for fabricating semiconductordevices, and particularly relates to a semiconductor device including agate insulating film made of a dielectric material having a highdielectric constant (hereinafter, referred to as a high-κ material) anda method for fabricating the device.

With recent increase in the integration degree and speed ofsemiconductor integrated circuit devices and expansion of thefunctionality thereof, the size of metal-oxide-semiconductor fieldeffect transistors (MOSFETs) has been reduced. As the thickness of agate insulating film decreases in accordance with this size reduction,the problem of increased gate leakage current caused by tunnel currentcomes to the surface. To solve this problem, there has been developed atechnique with which a high-κ material of metal oxide such as hafniumoxide (HfO₂) or zirconium oxide (ZrO₂) is used for a gate insulatingfilm so that the equivalent oxide thickness EOT is reduced with aphysical thickness increased. The equivalent oxide thickness EOT isherein a thickness calculated from the thickness of a film made of adielectric having a relative dielectric constant different from that ofsilicon oxide (SiO₂) in terms of the relative dielectric constant ofsilicon oxide.

In the initial stage of development, the use of a gate insulating filmmade of metal oxide such as HfO₂ or ZrO₂ causes a problem in which aninterface layer is formed between a silicon substrate and the gateinsulating film. This interface layer has a low dielectric constant, sothat the effective relative dielectric constant of the gate insulatingfilm decreases, i.e., the equivalent oxide thickness EOT increases.Therefore, it was necessary to suppress formation of such an interfacelayer as much as possible. However, once the formation of an interfacelayer was successfully suppressed so that a high effective relativedielectric constant of the gate insulating film is maintained, i.e., theequivalent oxide thickness EOT is reduced afterward, there arisesanother problem in which carrier mobility deteriorates as compared tothe case of a silicon oxide film and, consequently, desired operatingcurrent cannot be obtained. It has been considered that a cause of thisproblem is that (1) fixed charge included in a high-κ materialelectrically interferes with carriers in channel to cause the carriermobility to deteriorate or (2) carriers in channel are scattered by alattice in the high-κ material to cause the carrier mobility todeteriorate, for example. In Non-patent literature 1 (M. Hiratani, S.Saito, Y. Shimamoto, and K. Torii, “Effective Electron Mobility Reducedby Remote Charge Scattering in High-κ Gate Stacks”, Jpn. J. Appl. Phys.,Part 1 84, (2002), pp. 4512-4522), for example, a relationship betweenthe mobility and the thickness of a silicon oxide film formed at theinterface between a silicon substrate and a gate insulating film.According to this relationship, to avoid deterioration of the carriermobility, channel (a substrate) and a high-κ material (a gate insulatingfilm) are preferably separated from each other or a silicate structurein which a metal concentration in the entire high-κ material is reducedis preferably used. However, since the interface layer made of, forexample, a silicon oxide film has a low relative dielectric constant,the effective relative dielectric constant of the gate insulating filmextremely decreases, i.e., the equivalent oxide thickness EOT increases,in a case where the thickness of the interface layer is relatively largeor in the case of a silicate structure in which the metal concentrationis relatively low. Accordingly, each of a structure including aninterface layer and a structure having a reduced metal concentration hasa trade-off relationship with the case of not adopting these structures.

In addition, the use of a high-κ material for a gate insulating filmcauses another problem. That is, the absolute value of the thresholdvoltage V_(t) during transistor operation increases due to reaction atthe upper interface of the gate insulating film, i.e., reaction betweenmaterials for the gate electrode and the gate insulating film. Though acause of this problem is unclear, it is reported that exposure to ahigh-temperature process in a transistor process such as activationperformed on ions implanted in source/drain regions causes agate-electrode material and an gate-insulating-film material to reactwith each other, so that an effective work function of thegate-electrode material varies. This phenomenon is called Fermi-levelpinning. For example, in Non-patent literature 2 (C. Hobbs, L. Fonseca,V. Dhandapani, S. Samavedam, B. Taylor, J. Grant, L. Dip, D. Triyoso, R.Hegde, D. Gilmer, R. Garcia, D. Roan, L. Lovejoy, R. Rai, L. Hebert, H.Tseng, B. White, and P. Tobin, “Fermi level pinning at the polySi/metaloxide interface”, Proceedings of the 2003 Symposium on VLSI Technology,(2003), pp. 9-10), it is reported that in a case where a gate-electrodematerial is polysilicon, the effective work function of the material isfixed at a position near the midgap (i.e., the intermediate value ofband gap energy) of silicon and toward the conduction band, i.e., nearthe work function of n-type doped polysilicon, irrespective of the typeof the dopant for polysilicon and, as a result, the absolute value ofthe threshold voltage V_(t) of a pMOSFET using a p-type dopedpolysilicon electrode is considerably large. In addition, regarding thisFermi-level pinning, inversion capacitance of the pMOSFET greatlydecreases, which becomes a major obstacle to the use of a high-κmaterial for a gate insulating film and polysilicon for a gateelectrode.

As a means for avoiding Fermi-level pinning occurring when polysiliconis used for a gate electrode, a metal-gate transistor structure using ametal having an appropriate work function and a so-calledfull-silicidation (FUSI) gate transistor structure in which not only anupper portion but also the entire portion of a polysilicon gateelectrode is silicided has been proposed. However, for the metal-gatetransistor structure, even when a metal having a high melting point isused as a gate-electrode material, a high-temperature process such asactivation on source/drain regions is performed, so that Fermi-levelpinning occurs and a desired work function is not obtained. In a casewhere a semiconductor device has a complementary MOS structure (i.e., aCMOS structure) including a pMOSFET and an nMOSFET, a dual-metalstructure including metals having work functions appropriate for therespective pMOSFET and nMOSFET is needed. However, this structure hasthe problem of uneasiness of processes such as gate etching.

For the FUSI gate transistor structure, a high-temperature process suchas activation on source/drain regions is performed and then apolysilicon gate electrode is subjected to full-silicidation. In otherwords, polysilicon forming the gate electrode is replaced with metalsilicide. In this case, when a CMOS structure is adopted, metalsilicides having work functions appropriate for a pMOSFET and an nMOSFETare needed for the respective gate electrodes. In Non-patent literature3 (K. Takahashi, K. Manabe, T. Ikarashi, N. Ikarashi, T. Hase, T.Yoshihara, H. Watanabe, T. Tatsumi and Y. Mochizuki, “Dual WorkfunctionNi-Silicide/HfSiON Gate Stacks by Phase-Controlled Full-Silicidation(PC-FUSI) Technique for 45 nm-node LSTP and LOP Devices”, IEDM Tech.Dig., (2004), pp. 91-94), the possibility of controlling the workfunction by varying the proportions of metal nickel and silicon in metalsilicide is proposed. However, Fermi-level pinning still occurs in thiscase, and a desired work function is not obtained. Moreover, no specificprocess flows for implementing a CMOS structure are clarified. InNon-patent literature 4 (C. S. Park, B. J. Cho, L. J. Tang, and D. L.Kwong, “Substituted Aluminum Metal Gate on High-K Dielectric for LowWork-Function and Fermi-Level Pinning Free”, IEDM Tech. Dig., (2004),pp. 299-302), insufficient uniformity and poor yield of a FUSI gateprocess itself are reported.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to obtain a desiredwork function by suppressing reaction between a high-κ material and agate-electrode material that causes Fermi-level pinning so thatuniformity and yield are enhanced in a semiconductor device with a CMOSstructure, i.e., a dual-gate structure, that is a MOS transistorstructure using a fully-silicided gate or a metal gate, and particularlya CMOS semiconductor device using a high-κ material for a gateinsulating film.

To achieve the object, according to the present invention, in fullsilicidation of gate electrode made of silicon in a semiconductor devicehaving a CMOS transistor, the level difference between the work functionof the metal and the Fermi level of silicon is utilized in such a mannerthat when the work function of the metal is higher than the Fermi levelof silicon, the metal concentration in the gate electrode of a pMOSFETis set higher than that of an nMOSFET whereas when the work function ofthe metal is lower than the Fermi level of silicon, the metalconcentration in the gate electrode of the pMOSFET is set lower thanthat of the nMOSFET. A metal having a work function higher than theFermi level of silicon is used for at least the gate electrode of thepMOSFET, out of the pMOSFET and the nMOSFET.

Specifically, a first semiconductor device according to the presentinvention includes: an n-transistor including a first gate insulatingfilm made of a high-dielectric-constant material and a first gateelectrode fully silicided with a metal, the first gate insulating filmand the first gate electrode being formed in this order over asemiconductor region; and a p-transistor including a second gateinsulating film made of the high-dielectric-constant material and asecond gate electrode fully silicided with the metal, the second gateinsulating film and the second gate electrode being formed in this orderover the semiconductor region, wherein if the metal has a work functionlarger than a Fermi level in potential energy of electrons of silicon, ametal concentration of the second gate electrode is higher than that ofthe first gate electrode whereas if the metal has a work functionsmaller than the Fermi level of silicon, a metal concentration of thesecond gate electrode is lower than that of the first gate electrode.

In the first semiconductor device, when the work function of a metal ishigher than the Fermi level in potential energy of electrons of siliconis set higher than the metal concentration in the fully-silicided firstgate electrode, so that the metal having a Fermi level higher than thatof silicon forming the second gate electrode enables suppression ofFermi-level pinning occurring in the p-transistor.

In the first semiconductor device, the Fermi level is 4.6 eV.

In the first semiconductor device, the metal preferably contains nickelor platinum as a main component. Since nickel (Ni) and platinum (Pt)have work function higher than the Fermi-level of silicon, so that theseelements are preferable especially for the p-transistor of the presentinvention.

A second semiconductor device according to the present inventionincludes: an n-transistor including a first gate insulating film made ofa high-dielectric-constant material and a first gate electrode, thefirst gate insulating film and the first gate electrode being formed inthis order over a semiconductor region; and a p-transistor including asecond gate insulating film made of the high-dielectric-constantmaterial and a second gate electrode made of a conductive filmcontaining a first metal, the second gate insulating film and the secondgate electrode being formed in this order over the semiconductor region,wherein the first metal has a work function larger than a Fermi level inpotential energy of electrons of silicon.

In the second semiconductor device, the work function of the first metalforming the second gate electrode in the p-transistor is higher than theFermi level in potential energy of electrons of silicon, so thatFermi-level pinning occurring in the p-transistor is suppressed.

In the second semiconductor device, the first gate electrode ispreferably fully silicided with a second metal.

In the second semiconductor device, the first gate electrode ispreferably made of a conductive film containing a second metal.

In the second semiconductor device, the first metal preferably containsnickel or platinum as a main component.

In the first or second semiconductor device, thehigh-dielectric-constant material preferably contains at least one metalselected from the group consisting of silicon, germanium, hafnium,zirconium, titanium, tantalum, aluminum and a rare-earth metal.

In the first or second semiconductor device, a buffer film made of aninsulator is preferably formed between the first gate insulating filmand the first gate electrode and between the second gate insulating filmand the second gate electrode.

In this case, the buffer film is preferably made of silicon nitride,silicon oxide, titanium oxide or aluminum oxide.

A first method for fabricating a semiconductor device according to thepresent invention includes the steps of: forming an n-transistorincluding a first gate insulating film and a first gate electrode madeof silicon and a p-transistor including a second gate insulating filmand a second gate electrode made of silicon, on a semiconductor region;selectively forming a first metal film and a second metal film on thefirst gate electrode and the second gate electrode, respectively, suchthat the first metal film and the second metal film have differentareas; and performing a heat treatment on the first gate electrode andthe second gate electrode on which the first metal film and the secondmetal film have been formed, thereby fully siliciding each of the firstgate electrode and the second gate electrode, wherein in the step ofselectively forming the first and second metal films, if a metalconstituting the second metal film has a work function larger than aFermi level in potential energy of electrons of silicon, the secondmetal film is formed to have an area larger than that of the first metalfilm whereas if the metal constituting the second metal film has a workfunction smaller than the Fermi level of silicon, the second metal filmis formed to have an area smaller than that of the first metal film.

With the first method, in the step of selectively forming a metal filmfor full silicidation, when the work function of the metal constitutingthe second metal film provided on the p-transistor is higher than theFermi-level in potential energy of electrons of silicon, for example,the metal concentration in the second gate electrode is higher than thatof the first gate electrode in the step of siliciding the entireportions of the first and second gate electrodes. This is because thearea of the second metal film is made larger than that of the firstmetal film. Accordingly, the use of the metal having a Fermi levelhigher than that of silicon and a high metal concentration enablessuppression of Fermi-level pinning occurring in the p-transistorincluding the second gate electrode. In addition, the gate electrodesare silicided after patterning, pattern etching that has beenconventionally performed on gate films is unnecessary.

A second method for fabricating a semiconductor device according to thepresent invention includes the steps of: forming an n-transistorincluding a first gate insulating film and a first gate electrode madeof silicon and a p-transistor including a second gate insulating filmand a second gate electrode made of silicon, on a semiconductor region;forming a metal film on the first gate electrode and the second gateelectrode; and performing a heat treatment on the first gate electrodeand the second gate electrode on which the metal film has been formed,thereby fully siliciding each of the first gate electrode and the secondgate electrode, wherein in the step of forming the metal film, if ametal constituting the metal film has a work function larger than aFermi level in potential energy of electrons of silicon, the thicknessof a portion of the metal film located on the second gate electrode ismade larger than that on the first gate electrode whereas if the metalhas a work function smaller than the Fermi level of silicon, thethickness of the portion of the metal film located on the second gateelectrode is made smaller than that on the first gate electrode.

With the second method, in the step of selectively forming a metal filmfor full silicidation, when the work function of the metal forming themetal film is higher than the Fermi-level in potential energy ofelectrons of silicon, for example, the metal concentration in the secondgate electrode is higher than that of the first gate electrode in thestep of siliciding the entire portions of the first and second gateelectrodes. This is because the thickness of a portion of the metal filmlocated on the second gate electrode is made larger than that on thefirst gate electrode. Accordingly, the use of the metal having a Fermilevel higher than that of silicon and a high metal concentration enablessuppression of Fermi-level pinning occurring in the p-transistorincluding the second gate electrode. In addition, the gate electrodesare silicided after patterning, pattern etching that has beenconventionally performed on gate films is unnecessary.

In the second method, the step of forming the metal film preferablyincludes the step of selectively removing an upper part of a portion ofthe metal film located on one of the first and second gate electrodes sothat the thickness of the portion of the metal film is reduced.

A third method for fabricating a semiconductor device according to thepresent invention includes the steps of: forming an n-transistorincluding a first gate insulating film and a first gate electrode madeof silicon and a p-transistor including a second gate insulating filmand a second gate electrode made of silicon, on a semiconductor region;masking the first gate electrode and then forming a first metal film onthe second gate electrode; performing a heat treatment on the secondgate electrode on which the first metal film has been formed, therebyfully siliciding the second gate electrode; removing the mask and thenforming a second metal film on the first gate electrode; and performinga heat treatment on the first gate electrode on which the second metalfilm has been formed, thereby fully siliciding the first gate electrode,wherein in the step of siliciding the second gate electrode, if a metalconstituting the first metal film has a work function larger than aFermi level in potential energy of electrons of silicon, a metalconcentration of silicide in the silicided second gate electrode is sethigher than 50% whereas if the metal constituting the first metal filmhas a work function smaller than the Fermi level of silicon, the metalconcentration of silicide in the second gate electrode is set lower than50%.

With the third method, in the step of siliciding the second gateelectrode, when the work function of the metal forming the first metalfilm provided on the p-transistor is higher than the Fermi-level inpotential energy of electrons of silicon, for example, the metalconcentration in silicide in the silicided second gate electrode formingthe p-transistor is higher than 50%. Accordingly, the metal having aFermi level higher than that of silicon and having a high metalconcentration enables suppression of Fermi-level pinning occurring inthe p-transistor including the second gate electrode. In addition, thegate electrodes are silicided after patterning, pattern etching that hasbeen conventionally performed on gate films is unnecessary.

A fourth method for fabricating a semiconductor device according to thepresent invention includes the steps of: forming an n-transistorincluding a first gate insulating film and a first gate electrode madeof silicon and a p-transistor including a second gate insulating filmand a second gate electrode made of silicon, on a semiconductor region;selectively removing the gate electrode of one of the n-transistor andthe p-transistor; selectively forming a third gate electrode made of aconductive film containing a first metal for the transistor from whichthe gate electrode has been removed; forming a metal film made of asecond metal on the gate electrode of the other transistor; andperforming a thermal treatment on the gate electrode on which the metalfilm has been formed, thereby fully siliciding the gate electrode onwhich the metal film has been formed.

With the fourth method, the gate electrode of one of the n-transistorand the p-transistor is selectively removed, and then a third gateelectrode made of a conductive film containing a first metal isselectively formed for the transistor whose gate electrode has beenremoved. In this manner, the silicon second gate electrode of thep-transistor is replaced with the third gate film made of the conductivefilm containing the first metal, so that when the work function of thefirst metal is higher than the Fermi-level in potential energy ofelectrons of silicon, the third gate electrode containing the firstmetal and forming the p-transistor enables suppression of Fermi-levelpinning occurring in the p-transistor. In addition, the gate electrodesare silicided after patterning, pattern etching that has beenconventionally performed on gate films is unnecessary.

A fifth method for fabricating a semiconductor device according to thepresent invention includes the steps of: forming an n-transistorincluding a first gate insulating film and a first gate electrode madeof silicon and a p-transistor including a second gate insulating filmand a second gate electrode made of silicon, on a semiconductor region;selectively removing the second gate electrode of the p-transistor;selectively forming a third gate electrode made of a first conductivefilm containing a first metal for the p-transistor from which the secondgate electrode has been removed; selectively removing the first gateelectrode of the n-transistor; and selectively forming a fourth gateelectrode made of a second conductive film containing a second metal forthe n-transistor from which the first gate electrode has been removed.

With the fifth method, the second gate electrode of the p-transistor isselectively removed, and then a third gate electrode made of a firstconductive film containing a first metal is selectively formed for thep-transistor from which the second gate electrode has been removed. Inaddition, the first gate electrode of the n-transistor is selectivelyremoved, and then a fourth gate electrode made of a second conductivefilm containing a second metal is selectively formed in the n-transistorfrom which the first gate electrode has been removed. In this manner, inthe p-transistor including the third gate electrode made of the firstconductive film and the n-transistor including the fourth gate electrodemade of the second conductive film, the work functions of the first andsecond metals are optimized. For example, the work function of the firstmetal is set higher than the Fermi level of silicon and the workfunction of the second metal is set lower than the Fermi level ofsilicon, so that Fermi-level pinning occurring in the p-transistor andthe n-transistor is suppressed. In addition, the gate electrodes aremetallized after patterning, pattern etching that has beenconventionally performed on gate films is unnecessary.

In the first or third method, each of the first and second metal filmspreferably contains nickel or platinum as a main component.

In the second method, the metal film preferably contains nickel orplatinum as a main component.

In the fourth or fifth method, the first metal or the second metalpreferably contains nickel or platinum as a main component.

In the first method, the thickness ratio of the first metal film withrespect to the first gate electrode is preferably one or less, and thethickness ratio of the second metal film with respect to the second gateelectrode is preferably two or more.

In the second method, the thickness ratio of the portion of the metalfilm located on the first gate electrode with respect to the first gateelectrode is preferably one or less, and the thickness ratio of theportion of the metal film located on the second gate electrode withrespect to the second gate electrode is preferably two or more.

In the fifth method, out of the n-transistor and the p-transistor, thethickness ratio of the metal film with respect to the gate electrode onwhich the metal film has been formed is preferably one or less.

In the first or second method, the silicide in the first gate electrodepreferably has a silicon concentration higher than that in the secondgate electrode.

In the first through fifth methods, each of the first and second gateinsulating films is preferably made of a high-dielectric-constantmaterial.

In this case, the high-dielectric-constant material preferably containsat least one metal selected from the group consisting of silicon,germanium, hafnium, zirconium, titanium, tantalum, aluminum and arare-earth metal.

If each of the first and second gate insulating films is made of ahigh-dielectric-constant material, in the step of forming then-transistor and the p-transistor, a buffer film made of an insulator ispreferably formed between the first gate insulating film and the firstgate electrode and between the second gate insulating film and thesecond gate electrode. Then, the buffer film provided between thesilicon gate insulating film and the gate electrode enables suppressionof reaction between the gate insulating film and the gate electrodeduring a high-temperature process in the formation of source/drainregions, for example. In addition, damage on the gate insulating film ofa high-κ material during removal of silicon (polysilicon) gate electrodeand full silicidation is suppressed.

In this case, the buffer film is preferably made of silicon nitride,silicon oxide, titanium oxide or aluminum oxide.

In forming the buffer film, the step of forming the n-transistor and thep-transistor preferably includes, before formation of the buffer film,the step of performing a heat treatment on the first gate insulatingfilm made of the high-dielectric-constant material and the second gateinsulating film made of the high-dielectric-constant material.

With semiconductor devices and methods for fabricating the devicesaccording to the present invention, a dual-gate structure in whichfull-silicidation or metallization with metals having work functionssuitable for respective p- and n-transistors is performed is achievedfor a CMOS device using a high-κ material for a gate insulating film. Asa result, driving performances of transistors are enhanced.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A through 1H are cross-sectional views illustrating respectiveprocess steps of a method for fabricating a semiconductor deviceaccording to a first embodiment of the present invention in thefabrication order.

FIGS. 2A through 2J are cross-sectional views illustrating respectiveprocess steps of a method for fabricating a semiconductor deviceaccording to a second embodiment of the present invention in thefabrication order.

FIGS. 3A through 3K are cross-sectional views illustrating respectiveprocess steps of a method for fabricating a semiconductor deviceaccording to a third embodiment of the present invention in thefabrication order.

FIGS. 4A through 4L are cross-sectional views illustrating respectiveprocess steps of a method for fabricating a semiconductor deviceaccording to a fourth embodiment of the present invention in thefabrication order.

FIGS. 5A through 5K are cross-sectional views illustrating respectiveprocess steps of a method for fabricating a semiconductor deviceaccording to a fifth embodiment of the present invention in thefabrication order.

FIGS. 6A through 6F are cross-sectional views illustrating respectiveprocess steps of a method for fabricating a conventional MOSFETincluding a fully-silicided gate electrode.

FIG. 7 is a graph showing capacitor (CV) characteristics ofsemiconductor devices (MOSFETs) fabricated according to the firstthrough fifth embodiments and comparative examples.

FIG. 8A is a band diagram of silicon in a comparative example.

FIG. 8B is a band diagram showing Fermi-level pinning occurring inpolysilicon (a gate electrode) when a high-κ material is used for a gateinsulating film.

FIG. 8C is a band diagram showing the Fermi level in a semiconductordevice (MOSFET) including a silicided gate electrode with a varyingmetal concentration according to the first through third embodiments.

FIG. 9 is a graph showing a relationship between leakage current andtransconductance of MOSFETs fabricated according to the first throughfifth embodiments and comparative examples.

FIG. 10 is a graph showing measurement results on equivalent oxidethicknesses and threshold voltages of MOSFET using gate insulating filmsfabricated according to the first through fifth embodiments andcomparative examples.

FIGS. 11A and 11B show relationships between the absolute values ofleakage current and gate voltages of MOSFETs. FIG. 11A is a graph forMOSFETs according to a comparative example. FIG. 11B is a graph forMOSFETs according to the first embodiment.

DETAILED DESCRIPTION OF THE INVENTION Comparative Example

As a comparative example for embodiments of the present invention, amethod for fabricating a conventional MOSFET having a fully-silicidedgate electrode in which the entire portions of a gate insulating filmmade of a high-κ material and polysilicon are silicided will bedescribed with reference to FIGS. 6A through 6F.

First, as shown in FIG. 6A, an isolation film 12 serving as a shallowtrench isolation (STI) is selectively formed in an upper portion of asubstrate 11 made of silicon (Si) and having a principal surface whoseplane orientation is the (100) plane, for example. Subsequently, ionsare implanted in an upper portion of the substrate 11, thereby forming ap-well 13 for an nMOSFET and an n-well 13 for a pMOSFET. In this manner,a plurality of device regions are formed in the principal surface of thesubstrate 11. Thereafter, the surface of the substrate 11 is subjectedto known standard RCA cleaning and dilute hydrofluoric acid (HF)cleaning in this order. Then, heat treatment is performed on thesubstrate 11 at a temperature of about 600° C. to about 700° C. in anoxygen atmosphere, for example. In this manner, an underlying film (notshown) made of silicon oxide (SiO₂) and having a thickness of about 0.5nm is formed on the device regions in the substrate 11.

Next, a high-κ film 14 made of metal oxide such as hafnium silicate(Hf_(x)Si_(1-x)O₄) is deposited by, for example, a metal-organicchemical vapor deposition (MOCVD) process to a thickness of about 3 nmover the underlying film.

Thereafter, heat treatment is performed at a temperature of about 700°C. to about 1000° C. so as to make the high-κ film sustainable in acompensation step for deficiency caused by removal of a remainingimpurity such as carbon (C) or hydrogen (H) and nitriding and alsosustainable under a thermal budget in a subsequent high-temperatureprocess. The heating atmosphere at this time is preferably a nitrogen(N₂) atmosphere containing a trace amount of oxygen (O₂) or an ammonium(NH₃) atmosphere so as to prevent a large change in thickness of theunderlying film (the interface layer) between the substrate 11 and thehigh-κ film 14.

Then, a gate-electrode film 15 having a thickness of about 100 nm andmade of doped polysilicon and a hard-mask film 16 made of silicon oxideare deposited in this order over the high-κ film 14 by CVD processes.Subsequently, a resist mask 17 having a gate pattern is formed on thehard-mask film 16 by lithography.

Thereafter, as shown in FIG. 6B, the hard-mask film 16 through thehigh-κ film 14 are patterned in this order by dry etching using theresist mask 17. In this manner, a hard mask 16A is formed out of thehard-mask film 16, a gate electrode 15A is formed out of thegate-electrode film 15 and a gate insulating film 14A is formed out ofthe high-κ film 14.

Subsequently, as shown in FIG. 6C, ion implantation (extensionimplantation) is performed on an upper portion of the substrate 11 usingthe hard mask 16A. Then, side walls 18 made of silicon oxide are formedon both sides of the gate electrode 15A, and then ions are implantedagain in an upper portion of the substrate 11 using the side walls 18and the gate electrode 15A as a mask, thereby forming source/drainregions 19.

Then, as shown in FIG. 6D, an interlayer insulating film 20 made ofsilicon oxide is deposited by a plasma CVD process over the entiresurface of the substrate 11 including the hard mask 16A and the sidewalls 18. Subsequently, the upper face of the interlayer insulating film20 is planalized by, for example, a chemical mechanical polishing (CMP)process, thereby exposing the hard mask 16A.

Thereafter, as shown in FIG. 6E, the hard mask 16A, an upper portion ofthe interlayer insulating film 20 and upper portions of the side walls18 are etched back, thereby exposing the gate electrode 15A.Subsequently, a metal film 21 made of nickel (Ni) for silicidation ofthe gate electrode 15A is deposited over the interlayer insulating film20 from which the gate electrode 15A is exposed. Then, the whole gateelectrode 15A is silicided (full-silicidation) by known heat treatmentto be changed into a gate electrode 15B. Thereafter, the unreacted metalfilm 21 is removed by selective dry etching, for example, therebyobtaining a MOSFET including the fully-silicided gate electrode 15B asshown in FIG. 6F.

FIG. 7 shows a capacitance-voltage (CV) characteristic of the gateinsulating film 14A formed in this comparative example. In FIG. 7, theMOSFETs of this comparative example (▪ and □) including the gateinsulating films 14A made of hafnium silicate (HfSiON) and the gateelectrodes 15B made of nickel silicide (NiSi) is shown together with aconventional example ( and ◯) including gate insulating films made ofSiON and gate electrodes made of polysilicon (Poly-Si) and aconventional example (▴ and Δ) including gate insulating films made ofHfSiON and gate electrodes made of polysilicon (Poly-Si). In this graph,the ordinate represents the capacitance (pF/100 μm²) and the abscissarepresents the gate voltage V_(g) (V). Each of the gate insulating filmscontains nitrogen typified by SiON and HfSiON, as a result of nitriding.

In FIG. 7, with respect to the CV curve of the nMOSFET (represented by) including the SiON gate insulating film and the Poly-Si gateelectrode, the flat band voltage V_(tb) rises at about −1V at theaccumulation side (where the gate voltage V_(g)<0) and the thresholdvoltage V_(t) rises at about +0.2 V at the inversion side (where thegate voltage V_(g)>0). With respect to the CV curve of the pMOSFET(represented by ◯) including the SiON gate insulating film and thePoly-Si gate electrode, the flat band voltage V_(fb) rises at about+0.8V at the accumulation side (where the gate voltage V_(g)>0) and thethreshold voltage V_(t) rises at about =0.2 V at the inversion side(where the gate voltage V_(g)<0). In this case, the difference betweenthe flat band voltage V_(fb) and the threshold voltage V_(t) isassociated with 1.1 eV that is the band gap energy of silicon (Si).

The threshold voltage V_(t) corresponds to the threshold voltage V_(t)during transistor operation. Therefore, the absolute value of thethreshold voltage V_(t) is preferably as small as possible. Accordingly,the absolute value of the flat band voltage V_(fb) is preferably asclose to about 1 V as possible. This preferred state means that the workfunctions of the gate electrodes of the nMOSFET and pMOSFET, or n⁺polysilicon and p⁺ polysilicon, are close to the conduction band (4.05eV) and the valence band (5.17 eV) of silicon (Si), respectively, asshown in FIG. 8B. That is, the preferred state is n⁺ semiconductor andp⁺ semiconductor each having a shallow energy level apart from themidgap (i.e., the intermediate energy between the valence band E_(v) andthe conduction band E_(c)) of each of n⁺ polysilicon and p⁺ polysilicon.

However, as seen from FIG. 7, in the conventional example (representedby ▴ and Δ) including HfSiON gate insulating films and Poly-Si gateelectrodes, the absolute values of the flat band voltages V_(t) in boththe nMOSFET and pMOSFET, especially the pMOSFET, are small, so that theabsolute values of the threshold voltages V_(t) are large accordingly.This means that the effective work functions of n⁺ polysilicon and p⁺polysilicon forming the gate electrodes of the nMOSFET and pMOSFETrepresented by ▴ and Δ. are close to the midgap of silicon as indicatedby the vertical arrows in FIG. 8B and, more strictly, are pinnedslightly toward the conduction band E_(c). There are various theories onthis phenomenon, but it is basically considered that the phenomenonoccurs because of reaction between a gate-electrode material and metaloxide of a high-κ material caused by a thermal budget in a transistorprocess, which is Si-HfO₂ bonding in this case. This phenomenon iscalled Fermi-level pinning as described above.

On the other hand, in the nMOSFET and pMOSFET of this comparativeexample (represented by ▪ and □) including the gate insulating films 14Aof HfSiON and the gate electrodes 15B of NiSi, as shown in FIG. 8C,nickel silicide (NiSi) has a work function close to the midgap ofsilicon. Accordingly, as seen from FIG. 7, the absolute values of theflat band voltages V_(fb) in both the nMOSFET and the pMOSFET,especially the pMOSFET, are small, so that the absolute values of thethreshold voltages V_(t) increase accordingly.

As described above, though polysilicon and nickel silicide as componentsof a gate electrode inherently have different work functions,Fermi-level pinning still occurs. In addition, in consideration ofconformity with a CMOS process, gate electrodes of an nMOSFET and apMOSFET need to be made of electrode materials having respectivedifferent work functions, i.e., it is necessary to achieve a dual-gatestructure.

As seen from FIG. 7, in this comparative example (▪ and □), thecapacitances are larger than those in the conventional example ( and ◯)using polysilicon electrodes and are twice as large as those in theconventional example at the inversion side. Accordingly, because ofreduction of the equivalent oxide thickness EOT and increase of theinversion capacitance, enhancement of transistor (FET) drivability isexpected. It is considered that this is because the fully-silicided gateelectrode 15B made of NiSi substantially functions as a metal gate sothat depletion capacitance of the polysilicon electrode is eliminated.

FIG. 9 shows a relationship between leakage current J_(g) andtransconductance g_(m) of the nMOSFET fabricated in this comparativeexample. In this case, all the samples shown in FIG. 9 are measured. Theordinate represents leakage current J_(g) (A/cm²) and the abscissarepresents transconductance g_(m), (μA/V²). The transconductance g_(m)is an index of drivability during transistor operation, i.e., thedifferential value of ON current with respect to a gate voltage. Thetransconductance g_(m) is approximately inversely proportional to theequivalent oxide thickness EOT and proportional to carrier mobility. Asshown in FIG. 9, in the MOSFET () including the HfSiON gate insulatingfilm and the Poly-Si gate electrode, high-speed response with low powerconsumption, i.e., small leakage current J_(g) and high transconductanceg_(m), is expected, as compared to the MOSFET (◯) including an SiON filmas the gate insulating film. However, in the conventional example(represented by ) using a combination of the Poly-Si gate electrode andthe HfSiON gate insulating film, the transconductance g_(m) is lowerthan that in a conventional structure using SiON for a gate insulatingfilm with respect to the same leakage current. This is mainly because ofdeterioration of carrier mobility. On the other hand, in thiscomparative example (represented by ▴) using a combination of the NiSigate electrode and the HfSiON gate insulating film, the leakage currentj_(g) increases to some degree because of thickness reduction of thegate insulating film, but the transconductance g_(m) greatly increasesbecause of large increase of inversion capacitance shown in FIG. 7.Accordingly, at this point, drivability of the transistor is greatlyenhanced by introducing the fully-silicided gate electrode 15B. In FIG.9, a region at the right side of the conventional example (SiON)indicated by the arrow is a region where the transconductance g_(m) ishigher than that in the case of using SiO₂ (SiON) for a gate insulatingfilm with respect to the same leakage current.

FIG. 10 shows measurement results on the equivalent oxide thicknessesEOT and the absolute values of the threshold voltages V_(t) of theMOSFETs fabricated in the comparative example and the conventionalexamples for all the samples shown in FIG. 7. FIG. 10 shows that theequivalent oxide thickness EOT is reduced when HfSiON, which is a high-κmaterial, is used for a gate insulating film, as compared to theconventional structures using SiON for gate insulating films. However,the absolute values of the threshold voltages V_(t) of the nMOSFET andthe pMOSFET using HfSiON gate insulating films for polysiliconelectrodes are larger than those of the conventional structures usingSiON gate insulating films for polysilicon electrodes, because ofFermi-level pinning. Between these MOSFETs, the absolute value of thethreshold voltage V_(t) of the pMOSFET is especially large. In thenMOSFET and the pMOSFET of this comparative example using HfSiON gateinsulating films for the fully-silicided gate electrodes 15B, theabsolute values of the threshold voltages V_(t) are larger than those inthe conventional example using SiON for gate insulating films andPoly-Si for gate electrodes, and the absolute value of the thresholdvalue V_(t) of the pMOSFET is especially large. This is because nickelsilicide inherently having a work function closer to the midgap ofsilicon is used for the gate electrodes in this conventional example.

In a MOSFET, a large absolute value of the threshold voltage V_(t) meansthat an effective voltage is less likely to be applied by application ofa gate voltage V_(g). Accordingly, the MOSFET using a combination of agate electrode of polysilicon and a gate insulating film of a high-κmaterial (HfSiON) has electrical characteristics, includingtransconductance g_(m), inferior to those of the conventional MOSFETusing SiON for a gate insulating film. In addition, this comparativeexample using a combination of the fully-silicided gate electrode 15Band the gate insulating film 14A of a high-κ material is excellent intransconductance g_(m) but is poor in electrical characteristics becausethe threshold voltage V_(t) is higher than that of the conventionalMOSFET using SiON for a gate insulating film.

Furthermore, this comparative example using a combination of thefully-silicided gate electrode 15B and the gate insulating film 14A of ahigh-κ material has another problem of a larger absolute value ofleakage current J_(g) and greater variation thereof as shown in FIG.11A. This variation is observed to some extent in conventionalstructures using polysilicon electrodes, but is considered to be morepronounced by full silicidation. In addition, it is also necessary toenhance the durability of a high-κ film to a full silicidation process.

As described above, in the MOSFETs of the comparative example using acombination of the gate insulating films 14A of a high-κ material andthe fully-silicided gate electrodes 15B, the gate electrodes 15Bfunction as metal gates in effect and the transistor drivability due toincrease of inversion capacitance is enhanced, but the absolute valuesof the threshold values V_(t) are large due to the Fermi-level pinningdescribed above.

For the fully-silicided gate electrode 15B, it is supposed to bepossible to adjust the work function by changing the composition ofsilicide. However, in general, it is not easy to control the metalamount contributing silicidation in a MOSFET. This means that a processflow for implementing a dual gate structure needs to be developed forreasons different from those for conventional transistor processes usingmetal gate structure including metal materials. Originally, with a fullsilicidation process, it should be easy to avoid difficulty in gateetching involved in conventional techniques and also to avoidhigh-temperature processes that cause reaction between high-κ materialsand gate-electrode materials, which is considered to be a cause ofFermi-level pinning.

Hereinafter, embodiments of the present invention will be described withreference to the drawings. In the following embodiments, fabricationmethods for achieving different compositions of gate electrodes of annMOSFET and a pMOSFET, i.e., for implementing a so-called dual-gatestructure, in order to prevent Fermi-level pinning in a CMOS structureusing fully-silicided gates or metal gates.

EMBODIMENT 1

A method for fabricating a semiconductor device with a CMOS structureaccording to a first embodiment of the present invention will bedescribed with reference to FIGS. 1A through 1H.

First, as shown in FIG. 1A, an isolation film 102 serving as a shallowtrench isolation (STI) is selectively formed in an upper portion of asubstrate 101 made of silicon (Si) having a principal surface whoseplane orientation is the (100) plane, for example. Subsequently, ionsare implanted in an upper portion of the substrate 101, thereby forminga p-well 103A in an n-transistor region 1 and an n-well 103B in ap-transistor region 2. In this manner, a CMOS device region is formed inthe principal surface of the substrate 101. Thereafter, the surface ofthe substrate 101 is subjected to known standard RCA cleaning and dilutehydrofluoric acid (HF) cleaning in this order. Then, heat treatment isperformed on the substrate 101 whose surface has been cleaned, at atemperature of about 600° C. to about 700° C. in an oxygen atmosphere,for example. In this manner, an underlying film (not shown) made ofsilicon oxide (SiO₂) and having a thickness of about 0.5 nm is formed onthe CMOS device regions in the substrate 101.

Next, a high-κ film 104 made of metal oxide is deposited by, forexample, a metal-organic chemical vapor deposition (MOCVD) process to athickness of about 3 nm over the underlying film. Specifically, bubblingis performed by blowing a carrier gas containing, for example, nitrogen(N₂) into Hf (O—t—C₃H₇)₄ as a liquid Hf source and Si(O—t—C₃H₇)₄ as aliquid Si source. In this manner, a source gas in which the liquid Hfsource and the liquid Si source are in gaseous form is introduced into areaction chamber together with the carrier gas. Then, a high-κ film 104(i.e., a film made of a high-κ dielectric) made of hafnium silicate(Hf_(x)Si_(1-x)O₄) is deposited with the temperature in the chamber setat about 500° C., At this time, the Hf concentration x with respect toSi is appropriately changed by adjusting the supply amounts of the Hfsource and the Si source. The Hf concentration x is preferably in therange from about 0.3 to about 0.5.

Thereafter, heat treatment is performed at a temperature of about 700°C. to about 1000° C. so as to make the high-κ film sustainable under acompensation step for deficiency caused by removal of a remainingimpurity such as carbon (C) or hydrogen (H) and nitriding and under athermal budget in a subsequent high-temperature process. The heatingatmosphere at this time is preferably a nitrogen (N₂) atmospherecontaining a trace amount of oxygen (O₂) or an ammonium (NH₃) atmosphereso as to prevent a large change in thickness of the underlying filmbetween the substrate 101 and the high-κ film 104. Subsequently, in thefirst embodiment, to prevent Fermi-level pinning caused by reactionbetween a high-κ material forming a gate insulating film and aconductive material forming a gate electrode for achievement of adesired work function of the gate electrode and a process flowexhibiting excellent uniformity and a high yield, a buffer film 105 madeof an insulator is deposited by a CVD process to a thickness of about0.5 nm over the high-κ film 104 before deposition of a gate-electrodefilm made of polysilicon. The buffer film 105 may be made of siliconnitride (SiN), silicon oxide (SiO₂), titanium oxide (TiO₂) or aluminumoxide (Al₂O₃). Since titanium oxide has a relative dielectric constanthigher than that of silicon oxide, the use of titanium oxide reduces theequivalent oxide thickness EOT. The use of aluminum oxide allowsreduction of the threshold voltage V_(t) of a pMOSFET by negative fixedcharge. In this embodiment, a MOSFET using the buffer film 105 made ofsilicon oxide and a MOSFET not using the buffer film 105 are comparedwith each other in terms of electrical characteristics.

Subsequently, a gate-electrode film 106 made of phosphorus (P)-dopedpolysilicon with a thickness of about 100 nm and a hard-mask film 107made of silicon oxide with a thickness of about 80 nm are deposited inthis order by CVD processes over the buffer film 105. Then, resist masks108 having gate patterns for an nMOSFET and a pMOSFET are formed on thehard-mask film 107 by lithography.

Thereafter, as shown in FIG. 1B, the hard-mask film 107 through thehigh-κ film 104 are sequentially patterned by dry etching containingchlorine gas (Cl₂), for example, as a main component and using theresist masks 108. In this manner, hard masks 107A for n-type and p-type,respectively, are formed out of the hard-mask film 107, gate electrodes106A for n-type and p-type, respectively, are formed out of thegate-electrode film 106, and gate insulating films 104A for n-type andp-type, respectively, are formed out of the high-κ film 104. Then, ionimplantation (extension implantation) is performed on an upper portionof the substrate 101 using the hard masks 107A. Subsequently, side walls110 made of silicon oxide are formed on both sides of each of the gateelectrodes 106A, and then ions are implanted again in an upper portionof the substrate 101 using the side walls 110 and the gate electrodes106A as a mask, thereby forming n-type source/drain regions 111A in thenMOSFET region and p-type source/drain regions 111B in the pMOSFETregion. The extension implantation and source/drain implantation for annMOSFET are performed separately from the extension implantation andsource/drain implantation for a pMOSFET, though the order of implantingan n-type dopant and a p-type dopant is not limited.

Then, as shown in FIG. 1C, an interlayer insulating film 112 made ofsilicon oxide is deposited by a plasma CVD process over the entiresurface of the substrate 101 including the hard masks 107A and the sidewalls 110. Subsequently, the upper face of the interlayer insulatingfilm 112 is planalized by, for example, a chemical mechanical polishing(CMP) process, thereby exposing the hard masks 107A.

Thereafter, as shown in FIG. 1D, the hard masks 107A, an upper portionof the interlayer insulating film 112 and upper portions of the sidewalls 110 are etched back using an etching gas containing fluorocarbonas a main component, thereby exposing the gate electrodes 106A.

Subsequently, as shown in FIG. 1E, a metal film 113 made of nickel (Ni)for silicidation of the gate electrodes 106A is deposited by, forexample, a sputtering process to a thickness of about 100 nm over theinterlayer insulating film 112 from which the gate electrodes 106A areexposed. The metal film 113 may be made of platinum (Pt), instead ofnickel.

Then, as shown in FIG. 1F, resist patterns 114 are formed by lithographyto mask portions of the metal film 113 located on the n-type and p-typegate electrodes 106A. In this embodiment, the amounts of metal containedin respective portions of the metal film 113 to be left for silicidationon the gate electrodes 106A are changed according to the masked areas ofthe metal film 113. Specifically, the mask area on the p-type gateelectrode 106A is made larger than that on the n-type gate electrode106A. For example, the mask-area ratio (the mask amount at thep-side/the mask amount at the n-side) is approximately two to three.

Thereafter, the metal film 113 is patterned by dry etching usingchlorine gas with the resist patterns 114 used as a mask, therebyforming an n-side metal film 113 a for n-type silicide and a p-sidemetal film 113 b for p-type silicide having a plane area larger thanthat of the n-side metal film 113 a. Then, the resist patterns 114 areremoved by ashing, thereby obtaining a structure shown in FIG. 1G.

Subsequently, the substrate 101 is subjected to heat treatment at atemperature of about 300° C. to about 600° C. in a nitrogen atmospherefor about one minute, for example, with the n-side metal film 113 a andthe p-side metal film 113 b left thereon. In this manner, the whole gateelectrodes 106A are silicided (full silicidation) to be changed intogate electrodes 106B and 106C. Then, the unreacted metal film 113 isremoved by selective dry etching using chlorine gas, for example,thereby obtaining dual fully-silicided-gate transistors including thefully-silicided n-side gate electrode 106B and the fully-silicidedp-side gate electrode 106C having a metal concentration higher than thatof the gate electrode 106B, as shown in FIG. 111. Etching performed onthe unreacted metal film 113 is not limited to dry etching, and wetetching may be used.

In this manner, in the first embodiment, the area of a portion of themetal film 113 used for silicidation of the polysilicon gate electrode106A at the n-side is different from that at the p-side. i.e., the metalamount at the p-side is larger than that at the n-side. This enablescontrol of metal contents in the fully-silicided n-side and p-side gateelectrodes 106B and 106C and, consequently, allows control of workfunctions in the nMOSFET and the pMOSFET. In this embodiment, as shownin FIG. 8C, the composition of the n-side gate electrode 106B is NiSiand the composition of the p-side gate electrode 106C is Ni₃Si. Thismakes the work function of the p-side gate electrode 106C higher, sothat Fermi-level pinning is suppressed especially in the pMOSFET.

In the first embodiment, the metal concentration in nickel silicide isadjusted by utilizing the remaining area of the metal film 113 forsilicidation. If the thickness ratio between the polysilicon n-side gateelectrode 106A and the n-side metal film 113 a is one or less and thethickness ratio between the polysilicon p-side gate electrode 106A andthe p-side metal film 113 b is two or more, the metal concentration insilicide is more effectively adjusted.

FIGS. 7 and 10 show capacitor characteristics (CV characteristics),equivalent oxide thicknesses EOT and the absolute values of thresholdvoltages V_(t) of the nMOSFET including the gate electrode 106B made ofNiSi and the pMOSFET including the gate electrode 106C made of Ni₃Siboth fabricated in the first embodiment, together with the comparativeexample. First, in FIG. 7, in the case (represented by ▪ and *) ofhaving the same structure as that of the first embodiment and notincluding a buffer film 105 made of silicon oxide (SiO₂), the nMOSFET(▪) uses a combination of the HfSiON gate insulating film and the NiSigate electrode, which is the same as in the comparative example. On theother hand, in the pMOSFET (*) using a combination of the HfSiON gateinsulating film and the Ni₃Si gate electrode, the absolute value of theflat band voltage V_(fb) at the accumulation side (where the gatevoltage V_(g)>0) is somewhat large and the absolute value of thethreshold voltage V_(t) at the inversion side (where the gate voltageV_(g)<0) is somewhat small accordingly, as compared to the comparativeexample (represented by □) using a combination of the HfSiON gateinsulating film and the NiSi gate electrode. Therefore, the drivabilityof the transistor (FET) is enhanced in terms of the threshold voltageV_(t). However, as shown in FIG. 10, the threshold voltage V_(t) of thepMOSFET in this case is still high, so that it can be estimated thatFermi-level pinning occurs.

As shown in FIG. 10, in the MOSFETs of the first embodiment in which thebuffer film 105 of SiO₂ is provided between the gate insulating films104A made of a high-κ material and the gate electrodes 106B and 106C,the equivalent oxide thicknesses EOT increase because of the buffer film105 and the inversion capacitances decrease, as indicated by ♦ and ⋄ inFIG. 7. It is considered that this is because Fermi-level pinning issuppressed though the equivalent oxide thicknesses EOT increase, so thatthe original work function of nickel silicide is reflected. That is, asshown in FIG. 10, with respect to the MOSFETs using a combination of aHfSiON gate insulating film and a Ni_(x)Si gate electrode, the absolutevalue of the threshold voltage V_(t) is somewhat large in the nMOSFETbut is greatly reduced in the pMOSFET, as compared to the MOSFETs of thecomparative example and the examples having the same structure as thatof the first embodiment except for that no buffer film is provided,i.e., the MOSFETs using a combination of a HfSiON gate insulating filmand a NiSi gate electrode. Accordingly, as in the first embodiment, ifthe buffer film 105 made of a dielectric is provided between the gateinsulating film 104 and each of the gate electrodes 106B and 106C, theinversion capacitance decreases as the drivability of the transistor butthe threshold voltage V_(t) is expected to increase.

FIG. 9 shows a relationship between leakage current J_(g) andtransconductance g_(m) of an nMOSFET fabricated in the first embodiment,together with the comparative example and a structure including nobuffer film. As described above, the transconductance g_(m) issubstantially proportional to the inversion capacitance and carriermobility. As shown in FIG. 9, in the structure (▴) including thecomparative example in which no buffer film is provided, the leakagecurrent J_(g) increases to some extent because of effective decrease ofthe physical thickness but the transconductance g_(m) greatly increasesbecause of large increase of the inversion capacitance shown in FIG. 7.In this aspect, it is considered that the drivability of the transistoris greatly enhanced.

On the other hand, in the structure of the first embodiment (Δ)including the buffer film 105 of SiO₂, because of increase of thephysical thickness corresponding to the thickness of the buffer film105, the leakage current J_(g) and the inversion capacitance decrease tosome degree and the transconductance g_(m) also decreases to someextent. However, in this structure, sufficient transistor drivability ismaintained, as compared to the structures of the conventional example(represented by ◯ and ) using a combination of a polysilicon electrodeand a SiON or HfSiON gate insulating film.

With respect to the absolute value of the leakage current J_(g) andvariation thereof, significant improvement is made in the MOSFETs of thefirst embodiment including the buffer film 105, as shown in FIG. 11B.

As described above, with the method for fabricating a CMOS deviceincluding dual fully-silicided gate electrodes according to the firstembodiment, a dual gate structure in which the gate electrodes 106B and106C having different work functions are used for the respective nMOSFETand pMOSFET is achieved, so that the absolute values of the thresholdvoltages V_(t) are reduced. As a result, the drivability of thetransistors is enhanced. In particular, when the buffer film 105 isprovided between the gate insulating films 104A made of a high-κmaterial and the fully-silicided gate electrodes 106B and 106C,Fermi-level pinning is suppressed, so that the absolute values of thethreshold voltages V_(t) are reduced, the yield in full silicidation isincreased and the reliability of a CMOS device is enhanced.

The composition of nickel silicide forming the gate electrode 106B ofthe nMOSFET is not necessarily NiSi and the Si concentration may be 50%or more as represented by NiSi₂. The composition of nickel silicideforming the gate electrode 106C of pMOSFET is not necessarily Ni₃Si andthe Ni concentration may be 50% or more as represented by Ni₂Si.

EMBODIMENT 2

Hereinafter, a method for fabricating a semiconductor device having aCMOS structure according to a second embodiment of the present inventionwill be described with reference to FIGS. 2A through 2J. In FIGS. 2Athrough 2J, components also shown in FIGS. 1A through 1H are denoted bythe same reference numerals, and the description thereof will beomitted. The process steps shown in FIGS. 2A through 2D are the same asthose described in the first embodiment.

First, in the process step shown in FIG. 2D, hard masks 107A made ofsilicon oxide, an upper portion of an interlayer insulating film 112 andupper portions of side walls 110 in an n-transistor region 1 and ap-transistor region 2 are etched back with an etching gas containingfluorocarbon as a main component, thereby exposing gate electrodes 106A.

Next, as shown in FIG. 2E, a resist pattern 124 is formed on theinterlayer insulating film 112 in the n-transistor region 1 or thep-transistor region 2 by lithography to mask a portion of the interlayerinsulating film 112 in the n-transistor region 1 at this time.

Then, as shown in FIG. 2F, the upper portion of the polysilicon gateelectrode 106A exposed between the side walls 110 in the p-transistorregion 2 is selectively etched by dry etching using an etching gascontaining chlorine (Cl₂) or hydrogen bromide (HBr) as a main componentwith the resist pattern 124 used as a mask, thereby forming a lower gateelectrode 106 a. The thickness of the lower gate electrode 106 a ispreferably a half or less of the thickness of a metal film forsilicidation to be deposited on the lower gate electrode 106 a in asubsequent step.

Thereafter, as shown in FIG. 2G, the resist pattern 124 is removed, andthen a metal film 113 of nickel (Ni) for siliciding the gate electrode106A and the lower gate electrode 106 a is deposited by, for example, asputtering process to a thickness of about 100 nm over the interlayerinsulating film 112 from which the gate electrode 106A and the lowergate electrode 106 a are exposed: At this time the thickness of aportion of the metal film 113 located on the lower gate electrode 106 ais large, so that a thick portion 113 c is formed on the lower gateelectrode 106 a.

Subsequently, as shown in FIG. 211, a resist pattern 125 is formed onthe metal film 113 by lithography to mask a portion of the metal film113 in the p-transistor region 2 at this time.

Then, the metal film 113 is etched by dry etching using chlorine (Cl₂)as a main component with the resist pattern 125 used as a mask, therebyforming a thin portion 113 d in a portion of the metal film 113 in then-transistor region 1. Thereafter, the resist pattern 125 is removed byashing, thereby obtaining the structure shown in FIG. 21. The thicknessof the thin portion 113 d is preferably equal to or less than that ofthe n-side gate electrode 106A.

Subsequently, the substrate 101 is subjected to heat treatment at atemperature of about 300° C. to about 600° C. in a nitrogen atmospherefor about one minute, for example, with the metal film 113 including thethick portion 113 c and the thin portion 113 d formed thereon. In thismanner, the entire portions of the gate electrode 106A and the lowergate electrode 106 a are silicided (full silicidation) to be changedinto gate electrodes 106B and 106C. Thereafter, the unreacted metal film113 is removed by selective dry etching using chlorine gas, therebyobtaining dual fully-silicided-gate transistors including thefully-silicided n-side gate electrode 106B and the fully-silicidedp-side gate electrode 106C having a metal concentration higher than thatin the gate electrode 106B, as shown in FIG. 2J.

In the second embodiment, the thickness of a portion of the metal film113 for siliciding the polysilicon gate electrode 106A at the n-side isdifferent from that at the p-side, i.e., the metal amount at the p-sideis larger than that at the n-side. In this case, as described above, thethickness ratio of the thin portion 113 d of the metal film 113 withrespect to the gate electrode 106A is preferably one or less, and thethickness ratio of the thick portion 113 c of the metal film 113 withrespect to the lower gate electrode 106 a is preferably two or more.This enables control of the metal-content ratio between thefully-silicided n-side gate electrode 106B and the fully-silicidedp-side gate electrode 106C and, consequently, allows control of workfunctions between the nMOSFET and the pMOSFET. In this embodiment, asshown in FIG. 8C, the composition of the n-side gate electrode 106B isNiSi and the composition of the p-side gate electrode 106C is Ni₃Si.This makes the work function of the p-side gate electrode 106C higher,so that Fermi-level pinning is suppressed especially in the pMOSFET.

Electrical characteristics of the semiconductor device of the secondembodiment are similar to those of the first embodiment. However, themethod of the second embodiment further ensures formation of the p-sidegate electrode 106C having a metal concentration higher than that of then-side gate electrode 106B, as compared to the method of the firstembodiment.

In the second embodiment, as shown in FIG. 2F, an upper portion of thegate electrode 106A in the p-transistor region 2 is removed.Alternatively, an upper portion of the gate electrode 106A in then-transistor region 1 may be removed. In such a case, instead of nickelor platinum, tantalum (Ta) or titanium (Ti) may be used for the metalfilm 113. This is because the work function of tantalum is lower than4.61 eV, which is the energy at the midgap of silicon, so that the metalconcentration in the n-side gate electrode 106B is preferably higherthan that of the p-side gate electrode 106C for suppression ofFermi-level pinning in the nMOSFET.

EMBODIMENT 3

Hereinafter, a method for fabricating a semiconductor device having aCMOS structure according to a third embodiment of the present inventionwill be described with reference to FIGS. 3A through 3K. In FIGS. 3Athrough 3K, components also shown in FIGS. 1A through 1H are denoted bythe same reference numerals, and the description thereof will beomitted. The process steps shown in FIGS. 3A through 3C are the same asthose described in the first embodiment.

First, as shown in FIG. 3C, an interlayer insulating film 112 made ofsilicon oxide is deposited over the entire surface of a substrate 101including hard masks 107A and side walls 110. Subsequently, the upperface of the interlayer insulating film 112 is planarized by, forexample, a CMP process, thereby exposing the hard masks 107A.

Next, as shown in FIG. 3D, a resist pattern 124 is formed on theinterlayer insulating film 112 in an n-transistor region 1 or thep-transistor region 2 by lithography to mask the n-transistor region 1at this time.

Then, as shown in FIG. 3E, the hard mask 107A, an upper portion of theinterlayer insulating film 112 and upper portions of the side walls 110in the p-transistor region 2 are etched back by dry etching usingfluorocarbon as a main component with the resist pattern 124 used as amask, thereby exposing a p-side gate electrode 106A.

Thereafter, as shown in FIG. 3F, the resist pattern 124 is removed, andthen a first metal film 113 made of nickel (Ni) for siliciding thep-side gate electrode 106A is deposited by, for example, a sputteringprocess to a thickness of about 100 nm over the interlayer insulatingfilm 112 from which the hard mask 107A is exposed in the n-transistorregion 1 and the gate electrode 106A is exposed in the p-transistorregion 2.

Subsequently, the substrate. 101 is subjected to heat treatment at atemperature of about 300° C. to about 600° C. in a nitrogen atmospherefor about one minute, for example, with the first metal film 113 formedthereon. In this manner, the whole p-side gate electrode 106A issilicided (full silicidation) to be changed into a gate electrode 106C.Thereafter, the unreacted first metal film 113 is removed by selectivedry etching using chlorine gas, thereby obtaining a fully-silicidedp-side gate electrode 106C having a metal concentration (Niconcentration) exceeding 0.5 (50%) as shown in FIG. 3G.

Then, as shown in FIG. 3H, a resist pattern 125 is formed on theinterlayer insulating film 112 in the p-transistor region 2 bylithography to mask the interlayer insulating film 112 and the gateelectrode 106C at this time.

Thereafter, as shown in FIG. 3I, the hard mask 107A, an upper portion ofthe interlayer insulating film 112 and upper portions of the side walls110 in the n-transistor region 1 are etched back by dry etching usingfluorocarbon as a main component with the resist pattern 125 used as amask, thereby exposing the n-side gate electrode 106A.

Subsequently, as shown in FIG. 3J, the resist pattern 125 is removed,and then a second metal film 123 for siliciding the gate electrode 106Aand the gate electrode 106C is deposited by, for example, a sputteringprocess to a thickness of about 100 nm over the interlayer insulatingfilm 112 from which the n-side gate electrode 106A and the p-side gateelectrode 106C are exposed.

Then, the substrate 101 is subjected to heat treatment at a temperatureof about 300° C. to about 600° C. in a nitrogen atmosphere for about oneminute, for example, with the second metal film 123 formed thereon. Inthis manner, the whole n-side gate electrode 106A is silicided to bechanged into a gate electrode 106B. At the p-side, nickel atoms innickel silicide are further excessively introduced into the gateelectrode 106C. Thereafter, the unreacted second metal film 123 isremoved by selective dry etching using chlorine gas, thereby obtainingdual fully-silicided-gate transistors including the fully-silicidedn-side gate electrode 106B and the fully-silicided p-side gate electrode106C having a metal concentration higher than that of the gate electrode106B, as shown in FIG. 3K.

In the third embodiment, during silicidation of the polysilicon gateelectrodes 106A, the composition of nickel silicide is determinedthrough two silicidation processes performed on the p-side gateelectrode 106A shown in FIGS. 3F and 3J. Accordingly, in thisembodiment, as shown in FIG. 8C, the composition of the n-side gateelectrode 106B is NiSi and the composition of the p-side gate electrode106C is Ni₃Si. This makes the work function of the p-side gate electrode106C higher, so that Fermi-level pinning is suppressed especially in thepMOSFET.

Electrical characteristics of the semiconductor device of the thirdembodiment are similar to those of the first embodiment.

In the third embodiment, the composition of the p-side gate electrode106C is determined through the two silicidation processes shown in FIGS.3F and 3J. If the metal concentration in the gate electrode 106C ishigher than (50% or more of) that in silicon and the second silicidationprocess shown in FIG. 3J is unnecessary, this second silicidationprocess does not need to be performed. In such a case, it is sufficientto mask the p-side gate electrode 106C with a resist film or the likesuch that the proportion of metal in the p-side gate electrode 106C thathas excessively reacted with Ni in the second metal film 123 at theprevious step does not vary.

EMBODIMENT 4

Hereinafter, a method for fabricating a semiconductor device having aCMOS structure according to a fourth embodiment of the present inventionwill be described with reference to FIGS. 4A through 4L. In FIGS. 4Athrough 4L, components also shown in FIGS. 1A through 1H are denoted bythe same reference numerals, and the description thereof will beomitted. The process steps shown in FIGS. 4A through 4E are the same asthose described in the first embodiment.

First, as shown in FIG. 4E, a hard mask 107A, an upper portion of aninterlayer insulating film 112 and upper portions of side walls 110 in ap-transistor region 2 are etched back by dry etching using fluorocarbonas a main component with a resist pattern 124 used as a mask, therebyexposing a p-side gate electrode 106A.

Next, as shown in FIG. 4F, the polysilicon gate electrode 106A exposedbetween the side walls 110 in the p-transistor region 2 is selectivelyetched by dry etching using an etching gas containing chlorine (Cl₂) orhydrogen bromide (HBr) as a main component with the resist pattern 124used as a mask, thereby exposing a buffer film 105 formed under the gateelectrode 106A.

Thereafter, as shown in FIG. 4G, the resist pattern 124 is removed, andthen a first metal film 115 made of platinum (Pt) for metallizing thep-side gate electrode is deposited by, for example, a sputtering or CVDprocess to a thickness of about 20 nm over the interlayer insulatingfilm 112 from which a hard mask 107A is exposed in an n-transistorregion 1 and the buffer film 105 is exposed in the p-transistor region2.

Subsequently, as shown in FIG. 4H, a resist pattern 125 is formed on thefirst metal film 115 by lithography to mask a portion of the first metalfilm 115 located in the p-transistor region 2.

Then, as shown in FIG. 4I, the first metal film 115 is etched back to beremoved by dry etching using chlorine as a main component with theresist pattern 125 used as a mask. Subsequently, the hard mask 107A, anupper portion of the interlayer insulating film 112 and upper portionsof side walls 110 in the n-transistor region 1 are etched back by dryetching using fluorocarbon as a main component, thereby exposing ann-side gate electrode 106A. In this manner, a metal-gate film 115 a isformed out of the first metal film 115 in the p-transistor region 2.This metal-gate film 115 a covers the inner bottom and wall of a recessformed by the two side walls 110 and the buffer film 105.

Thereafter, as shown in FIG. 4J, the resist pattern 125 is removed, andthen a second metal film 116 made of nickel (Ni) for siliciding then-side gate electrode 106A is deposited by, for example, a sputteringprocess to a thickness of about 100 nm over the interlayer insulatingfilm 112 from which the n-side gate electrode 106A and the p-sidemetal-gate film 115 a are exposed.

Subsequently, as shown in FIG. 4K, a substrate 101 is subjected to heattreatment at a temperature of about 300° C. to about 600° C. in anitrogen atmosphere for about one minute, for example, with the secondmetal film 116 formed thereon. In this manner, the whole n-side gateelectrode 106A is silicided to be changed into a gate electrode 106B. Atthe same time, a gate electrode 106D made of an alloy of platinum andnickel is formed out of the p-side gate-electrode film 115 a.

Then, the unreacted first and second metal films 115 and 116 are removedby selective dry etching using chlorine gas, thereby obtaining dualfully-silicided-gate transistors including the fully-silicided n-sidegate electrode 106B and the metallized p-side gate electrode 106D, asshown in FIG. 4L.

In the fourth embodiment, a portion of the p-side gate-electrode film115 a is changed into an alloy through the full silicidation shown inFIG. 4K. Accordingly, for the p-side gate electrode 106D, the workfunction of the gate electrode 106D that has been changed into an alloyitself needs to be considered as a design value or the gate-electrodefilm 115 a (the first metal film 115) needs to be deposited to have alarge thickness so as to prevent a portion in contact with the gateinsulating film 104A as well as the buffer film 105 from changing intoan alloy. In addition, before deposition of the second metal film 116for silicidation shown in FIG. 4J, a protection film made of, forexample, titanium nitride (TiN) needs to be deposited as analloy-preventing layer over the gate-electrode film 115 a.

In the nMOSFET, the thickness ratio of the second metal film 116 withrespect to the gate electrode 106A is preferably one or less. Then, theNi concentration in nickel silicide (NiSi) forming the fully-silicidedn-side gate electrode 106B is set at 50% or less.

In the fourth embodiment, the p-side gate electrode 106D is metallizedby using platinum and nickel. Conversely, the n-side gate electrode 106Cmay be metallized and the p-side gate electrode 106D may be fullysilicided. In such a case, instead of platinum, tantalum (Ta), titanium(Ti) or nitrides containing these elements can be used for the firstmetal film 115.

Electrical characteristics of the MOSFETs forming the semiconductordevice of the fourth embodiment will be described in the following fifthembodiment.

EMBODIMENT 5

Hereinafter, a method for fabricating a semiconductor device having aCMOS structure according to a fifth embodiment of the present inventionwill be described with reference to FIGS. 5A through 5K. In FIGS. 5Athrough 5K, components also shown in FIGS. 1A through 1H are denoted bythe same reference numerals, and the description thereof will beomitted. The process steps shown in FIGS. 5A through 5C are the same asthose described in the first embodiment.

First, as shown in FIG. 5C, an interlayer insulating film 112 made ofsilicon oxide is deposited over the entire surface of a substrate 101including hard masks 107A and side walls 110. Subsequently, the upperface of the interlayer insulating film 112 is planarized by, forexample, a CMP process, thereby exposing the hard masks 107A.

Next, as shown in FIG. 5D, a resist pattern 124 is formed on theinterlayer insulating film 112 in an n-transistor region 1 or ap-transistor region 2 by lithography to mask the p-transistor region 2at this time.

Then, as shown in FIG. 5E, the hard mask 107A, an upper portion of theinterlayer insulating film 112 and upper portions of the side walls 110in the n-transistor region 1 are etched back by dry etching usingfluorocarbon as a main component with the resist pattern 124 used as amask, thereby exposing an n-side gate electrode 106A.

Thereafter, as shown in FIG. 5F, the polysilicon gate electrode 106Aexposed between the side walls 110 in the n-transistor region 1 isselectively etched by dry etching using an etching gas containingchlorine (Cl₂) or hydrogen bromide (HBr) as a main component with theresist pattern 124 used as a mask, thereby exposing a buffer film 105under the gate electrode 106A.

Subsequently, as shown in FIG. 5G, the resist pattern 124 is removed,and then a conductive film 117 made of tantalum silicon nitride (TaSiN)for matallizing the n-side gate electrode is deposited by, for example,a sputtering or CVD process to a thickness of about 20 nm over theinterlayer insulating film 112 from which the buffer film 105 is exposedin the n-transistor region 1 and the hard mask 107A is exposed in thep-transistor region 2.

Then, as shown in FIG. 5H, a resist pattern 125 is formed on theconductive film 117 by lithography to mask a portion of the conductivefilm 117 located in the n-transistor region 1.

Thereafter, as shown in FIG. 5I, the conductive film 117 is etched backto be removed by dry etching using chlorine as a main component with theresist pattern 125 used as a mask. Subsequently, the hard mask 107A, anupper portion of the interlayer insulating film 112 and upper portionsof the side walls 110 in the p-transistor region 2 are etched back bydry etching using fluorocarbon as a main component, thereby exposing thep-side gate electrode 106A. Then, the polysilicon gate electrode 106Aexposed between the side walls 110 in the p-transistor region 2 isselectively etched by dry etching using an etching gas containingchlorine (Cl₂) or hydrogen bromide (HBr) as a main component, therebyexposing the buffer film 105 under the gate electrode 106A. In thismanner, a metal-gate film 117 a is formed out of the conductive film 117in the n-transistor region 1. This metal-gate film 117 a covers theinner bottom and wall of a recess formed by the two side walls 110 andthe buffer film 105.

Then, as shown in FIG. 5J, the resist pattern 125 is removed, and then ametal film 118 made of platinum (Pt) for metallizing the p-side gateelectrode is deposited by, for example, a sputtering process to athickness of about 20 nm over the interlayer insulating film 112 fromwhich the n-side metal-gate film 117 a and the p-side buffer film 105are exposed.

Thereafter, as shown in FIG. 5K, the unreacted conductive film 117 andmetal film 118 are removed by selective dry etching using chlorine gasand a CMP process, thereby obtaining dual fully-silicided-gatetransistors including an n-side gate electrode 106E metallized by usingTaSiN and Pt and a p-side gate electrode 106D metallized by using Pt.

In the fifth embodiment, a portion of the n-side gate-electrode film 117a is changed into an alloy through the p-side metal-gate formation shownin FIG. 5J. Accordingly, for the n-side gate electrode 106E, the workfunction of the gate electrode 106E changed into an alloy itself needsto be considered as a design value or the gate-electrode film 117 a (theconductive film 117) needs to be deposited to have a large thickness soas to prevent a portion in contact with the gate insulating film 104A aswell as the buffer film 105 from changing into an alloy. In addition,before deposition of the metal film 118 shown in FIG. 5J, a protectionfilm made of, for example, titanium nitride (TiN) needs to be depositedas an alloy-preventing layer over the gate-electrode film 117 a.

Hereinafter, characteristics of the semiconductor device of the fifthembodiment will be described with reference to the drawings togetherwith characteristics of the semiconductor device of the fourthembodiment.

FIGS. 7 and 10 show capacitor characteristics (CV characteristics), theequivalent oxide thicknesses EOT and the absolute values of thethreshold voltages V_(t) of the nMOSFETs including the gate electrodes106B and 106E and pMOSFETs including the gate electrodes 106D fabricatedin the fourth and fifth embodiments, together with the comparativeexample. The nMOSFET represented by ♦ and the pMOSFET represented by ⋄correspond to the fourth embodiment, and the nMOSFET represented by −and the pMOSFET represented by + correspond to the fifth embodiment.

In a structure in which no buffer film 105 made of silicon oxide (SiO₂)is provided between a gate insulating film and a gate electrode, a metalmaterial forming the gate electrode and a high-κ material of metal oxideforming the gate insulating film react with each other, resulting inthat even a noble metal such as platinum cannot obtain its original workfunction and the threshold voltage V_(t) tends to increase. Accordingly,it is estimated that Fermi-level pinning occurs. However, in a structurein which the buffer film 105 is provided, the equivalent oxidethicknesses EOT of both the nMOSFET and the pMOSFET increase as shown inFIG. 10. As shown in FIG. 7, this increase of the equivalent oxidethicknesses EOT causes the inversion capacitances of both the nMOSFETand the pMOSFET to decrease. That is, though the equivalent oxidethicknesses EOT increase, the original work functions are reflected. Itseems that this is because Fermi-level pinning is suppressed. Theabsolute values of the threshold voltages V_(t) of the nMOSFETrepresented by − and the pMOSFET represented by + are smaller than thoseof the nMOSFET of the comparative example and the first through fourthembodiments represented by ♦ and the pMOSFET of the first through thirdembodiments represented by ⋄.

In this manner, in the fifth embodiment, as the drivability of atransistor, the inversion capacitance is reduced because of provision ofthe buffer film 105, but a capacitance value much larger than that inthe structure of the conventional example () is maintained.Accordingly, in the semiconductor device of the fifth embodiment,increase of the threshold voltages V_(t) is suppressed, so that furtherimprovement in electrical characteristics is expected.

FIG. 9 shows a relationship between leakage current J_(g) andtransconductance g_(m) of the nMOSFET fabricated in the fifthembodiment, together with the structures of the comparative example andother embodiments. As described above, the transconductance g_(m) issubstantially proportional to the inversion capacitance and the carriermobility. Accordingly, the leakage current J_(g) and thetransconductance g_(m) of the structure of the fifth embodiment (□) arealmost equal to those in the structure of another embodiment (Δ).Therefore, the drivability of a transistor is sufficiently greater thanthat in the conventional structure (◯) in which a polysilicon electrodeand a SiON gate insulating film are combined.

In addition, the MOSFETs of the fifth embodiments exhibit the mostexcellent electrical characteristics in total because increase in theabsolute values of the threshold voltages V_(t) is suppressed, as shownin FIG. 10.

As described above, with the method for fabricating a semiconductordevice having a CMOS structure according to the fifth embodiment, a dualgate structure in which metal gate electrodes having different workfunctions are provided for an nMOSFET and a pMOSFET, respectively, isimplemented, and the increase of threshold voltages V_(t) duringtransistor operation is sufficiently suppressed. As a result, thedrivability of transistors is greatly enhanced.

With a semiconductor device and a method for fabricating the deviceaccording to the present invention, a dual gate structure in whichfull-silicidation or metallization is performed by using metals havingwork functions suitable for respective p- and n-transistors is achievedfor a CMOS device using a high-κ material for a gate insulating film.Therefore, the present invention is useful for a CMOS device including agate insulating film made of a high-κ material and a method forfabricating the device.

1-48. (canceled)
 49. A method for fabricating a semiconductor device,the method comprising steps of: forming on a semiconductor region ann-transistor including a first gate insulating film and a first gateelectrode made of silicon and a p-transistor including a second gateinsulating film and a second gate electrode made of silicon; selectivelyremoving the second gate electrode of the p-transistor; selectivelyforming a third gate electrode for the p-transistor from which thesecond gate electrode has been removed, the third gate electrode beingmade of a first conductive film containing a first metal; selectivelyremoving the first gate electrode of the n-transistor; and selectivelyforming a fourth gate electrode for the n-transistor from which thefirst gate electrode has been removed, the fourth gate electrode beingmade of a second conductive film containing a second metal.
 50. Themethod of claim 49, wherein the first metal or the second metal containsnickel or platinum as a main component.
 51. The method of claim 49,wherein each of the first and second gate insulating films is made of ahigh-dielectric-constant material.
 52. The method of claim 51, whereinthe high-dielectric-constant material contains at least one metalselected from the group consisting of silicon, germanium, hafnium,zirconium, titanium, tantalum, aluminum and a rare-earth metal.
 53. Themethod of claim 51, wherein in the step of forming the n-transistor andthe p-transistor, a buffer film is formed between the first gateinsulating film and the first gate electrode and between the second gateinsulating film and the second gate electrode.
 54. The method of claim53, wherein the buffer film includes nitrogen, titanium, or aluminum.55. The method of claim 53, wherein the step of forming the n-transistorand the p-transistor includes, before formation of the buffer film, astep of performing heat treatment on the first gate insulating film madeof the high-dielectric-constant material and the second gate insulatingfilm made of the high-dielectric-constant material.